The present invention relates generally to the field of magnetic data storage devices. More particularly, the present invention relates to partial response, maximum likelihood read/write channels for magnetic data storage designs.
Digital data processed by computers are often stored by a permanent data storage system, referred to as a hard disk or hard disk drive. The data generally consists of streams of 1""s and 0""s (xe2x80x9cbitsxe2x80x9d). The hard disk includes a magnetic surface in which discrete magnetic fields can be programmed to represent the bits of data. In conventional hard disk designs, the stream of data is encoded and then programmed to the hard disk via a read/write head that passes over the magnetic surface. As the read/write head passes the magnetic surface, the read/write head polarizes segments of the surface to one of two magnetic field polarities. Thus, the encoded bits include a stream of magnetic field reversals.
Because the data is encoded as field reversals, it is desirable to locate a specific segment of the magnetic surface for individual bits. Runs of consecutive segments having the same polarity are undesirable because of difficulty with determining where one bit ends and where another begins. To keep track of bit location, clock synchronization data is encoded with the programmed data. The clock synchronization data provides references (xe2x80x9cClock Referencesxe2x80x9d) when the data is read from the hard drive. However, the clock references use valuable space on the magnetic surface.
Data has generally been read using peak detection. When the read/write head passes a reversal in the magnetic field, a small voltage spike may be imparted on the read/write head. A peak detection read circuit, referred to as a read/write channel, is electrically coupled with the read/write head passing over the magnetic surface. The read/write channel interprets data read from the detected peaks based on encoding techniques used to program the data. The read/write channel converts the signal to digital information by continuously analyzing the data in synchronization with a clock and identifying the voltage spikes representing the magnetic field reversals.
The density in which data can be stored with peak detection methods is limited due to, for example, interference of closely packed magnetic peaks. Due to the limited physical space on the hard disk, the amount of stored data is optimized by increasing the areal density in which the data can be stored. However, the goal of optimizing the density of the data stored on the hard disk is balanced with optimizing the reliability of the data read from the disk. As the density increases, the intricacy with which individual data bits are distinguished and with which data is isolated from any background noise increases. As the density increases, the possibility of inter-symbol interference (xe2x80x9cISIxe2x80x9d) increases. Specifically, as the density increases, the strength of individual magnetic fields decreases.
Read/write channels based on partial response, maximum likelihood
(xe2x80x9cPRMLxe2x80x9d) methods provide reliable data storage at increased densities, while requiring minimal clock references. This technology generally includes a two-part process: 1) Partial Response, and 2) Maximum Likelihood. For the partial response aspect, a read/write channel circuit implements complex digital signal processing (xe2x80x9cDSPxe2x80x9d) and sampling algorithms to manipulate the stream of magnetic data coming from the read/write head. For the Maximum likelihood aspect, the read/write channel is configured to determine the most likely sequence of data that the stream of magnetic data represents. The stream of magnetic data from the read/write head is decoded in a process referred to as Viterbi Detection. During Viterbi Detection, an algorithm determines possible combinations of data, and the match with a least difference is the combination determined to have the maximum likelihood of being the correct data.
PRML read/write channels often include one or more oscillator circuits providing a multiphase clock signal used for synchronizing read and write operations. In general, the oscillator provides multiple clock pulse waves, each having substantially the same frequency and out of phase with respect to the other clock pulse waves. At power up, the oscillator often provides the clock pulse waves in random order. However, other circuits in the read/write channel provided with the clock signal require the multiphase clock signal to be provided in a predictable order. Specifically, the clock signal pulse waves having a zero phase start are sequentially provided according to respective phase for each clock signal pulse wave.
Circuits have been added to the oscillator to ensure a zero phase start. However, circuits added to the oscillator produce distortion in the multiphase clock pulse waves and slow the speed at which the oscillator can generate the multiphase clock signal. In addition, when the multiphase clock signal is reset, the oscillator circuit is reset, additionally requiring reset of any circuits relying on the multiphase clock signal. Other techniques for providing a zero phase restart include resetting the multiphase clock signal in one period of the pulse wave while slowing the clock pulse. This technique however, requires significant time and precise clock delay compensation.
Accordingly, there is a need in the art for a programmable high-speed zero phase restart circuit for a multiphase clock.
A high speed zero phase restart for a multiphase clock is disclosed. The high speed zero phase restart for a multiphase clock provides quick and reliable synchronization of pulse waves. The multiple pulse waves are sequentially coupled to terminals corresponding to the pulse wave, according to the pulse wave phase.
One embodiment of a high speed zero phase restart apparatus comprises an integrated circuit having an input, an output and a zero phase circuit. The input is configured to receive multiple clock pulse waves generated by a multiphase clock signal. Each clock pulse wave has substantially the same frequency and is out of phase with respect to the other clock pulse waves. The output includes output terminals, including at least one corresponding terminal for each of the clock pulse waves. The zero phase circuit is electrically coupled to both the input and the output. In response to a reset signal, the zero phase circuit sequentially in time couples each of the clock pulse waves to corresponding output terminals. The pulse waves are sequentially coupled so that a most-significant-phase clock pulse wave is the first signal coupled to the corresponding output and a least-significant-phase clock pulse wave is the last clock pulse wave coupled to the corresponding output terminal. After the pulse wave is coupled to the corresponding output, the output remains coupled until another reset signal is received at the zero phase circuit.
One embodiment of a method for a high speed zero phase restart includes restarting a multiphase clock signal by receiving a plurality of clock pulse waves; coupling a most-significant-phase clock pulse wave to a most-significant output terminal in response to a reset input signal; coupling at least one intermediate-phase clock pulse wave to an intermediate output terminal in response to coupling the most significant phase clock pulse wave; and coupling a least-significant-phase clock pulse to a least significant output terminal in response to coupling the intermediate phase clock pulse wave.
The foregoing discussion of the summary of the invention is provided only by way of introduction. Nothing in this section should be taken as a limitation on the claims, which define the scope of the invention. Additional objects and advantages of the present invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the claims.